High Performance and Energy Efficient SRAM-based Architecture for TCAM

Content addressable memory (CAM) is a type of solid-state memory in which data is provided as input and an operation is performed to returns the address as output. Unlike other memories (SRAM, DRAM), it performs the search operation in parallel on complete location at once, offered significant reduction in searching time. A ternary content addressable memory (TCAM) is a specialized CAM design for fast table lookups and adds masking capabilities by storing and searching a third “don‟t care” state. Hence, it is attractive for applications such as packet forwarding and classification in network routers. But TCAMs have some limitations such as low storage density, relatively slow access time, low scalability, complex circuitry, and are very expensive, when compared with static random access memories (SRAMs). Consequently, in order to make use of SRAM benefits in TCAMs and conquer the limitations of TCAM, SRAM can be configured with additional logic to behave like ternary CAM memory. This can be achieved by means of hybrid partitioning the TCAM table and mapping it into corresponding SRAM memory location. In proposed method, a Parameter Extractor is used in modified architecture. The purpose of Parameter Extractor is to minimize the number of comparisons during search operation. As the number of comparison operation is reduced, the power consumption of memory operation is reduced considerably, thus providing an efficient architecture.